Its value is derived from what is being driven from its driver(s). The distinction comes from how they are intended to represent different hardware structures.Ī net data type represents a physical connection between structural entities (think a plain wire), such as between gates or between modules. Verilog data types are divided into two main groups: nets and variables. Verilog data types, Verilog reg, Verilog wire Read on for my discovery of the differences between Verilog reg, Verilog wire, and SystemVerilog logic. I dug into the language reference manual, searched for the now-defunct Verilog-2005 standard document, and got into a bit of history lesson. So I decided to find out exactly how these data types worked to write this article. That again generally worked, but every now and then I would run into a cryptic error message about variables, nets, and assignment. Then when I adopted SystemVerilog for writing RTL designs, I was told everything can now be “type logic”. Use Verilog wire for LHS of signals assigned outside always blocks.Use Verilog reg for left hand side (LHS) of signals assigned inside in always blocks.As a beginner, I was told to follow these guidelines, which seemed to generally work: The difference between Verilog reg and Verilog wire frequently confuses many programmers just starting with the language (certainly confused me!).